ECET 365

Text: Brown and Vranesic, Fundamentals of Digital Logic with VHDL Design, 3rd Ed., McGraw-Hill.

Week

Date

Reading

Topics & Activities

Homework &

Project due dates

9/4

1.1 – 1.6

2.1 - 2.6

Introduction to Combinational Logic,

Boolean Algebra, Gates, Logic Diagrams

#1 Ch. 2: 1, 2, 7, 8, 20, 31, 32

9/8 ,9/11

2.7 ,

4.1 - 4.5

NAND & NOR implementations,

Simplification of Expressions, Truth Tables,

K-maps, Don’t cares, Multi-output synthesis and analysis

#2 Ch. 4: 1 - 5, 10, 12

First Software Assignment Due

9/15,9/18

2.8 -2.12

3.1 - 3.3

Introduction to multiplexers,

Introduction to CAD tools and VHDL,

NMOS and CMOS gates

#3 Ch. 2: 44, 45, 47

Ch. 3: 1, 2, 3

4, 5

9/22,9/25

9/29,10/2

3.9

6.1 - 6.4

6.6 - 6.8

Transmission Gates, Decoders, Encoders, Multiplexers, Shannon's Expansion

VHDL for Combinational Circuits

#4 Ch. 6: 1 – 6 (Do not need to use 2:1 MUXs)

Project 1 due

10/6,10/9

3.8

4.6

Electrical Considerations

Multi-level logic

Instructor Assigned Problems

10/13,10/16

5.1 - 5.3, 5.5

6.5, 9.6

Arithmetic Logic, Comparators

Hazards and Glitches

#5 Ch. 5: 1, 3, 4, 5, 17

Ch. 6: 19, 20, 24

Ch. 9: 10, 12

Project 2 due

10/20,10/23

3.6, 3.10

Notes

ROMs & PROMs

Programmable Logic Devices

#6 Ch. 3: 36 – 38 Last day to submit Journal report.

10/27,10/30

7.1 - 7.7

Introduction to Sequential Logic

Latches and Flip Flops

#7 Ch. 7: 1, 4, 6, 8

11/3,11/6

Latches and Flip Flops Continued

#8 Ch. 7: 10, 11

Project 3 due.

11/10,11/13

7.8 - 7.12

Registers & Counters, VHDL & CAD tools

#9 Ch. 7: 15, 16,24 Last day to submit Meeting report.

11/17, 11/20

8.9

Analysis of Sequential Logic

State, Transition, and Excitation Tables

State Diagrams

#10 Ch. 8: 29

13,14

11/24,12/1, 12/4, 12/8

8.1 - 8.7

Design of Sequential Logic: Counters, Universal Counters, Sequence Detectors, State Reduction, Binary Assignment, Excitation Equations

#11 Ch. 8: 1 - 3, 5, 6, 20 – 22, 29, 30

Project 4 due.

TAC of ABET stands for the Technology Accreditation Commission of ABET, 111 Market Place, Suite 105, Baltimore, MD 21202-4012. Telephone (410) 347-7700

TAC of ABET Criterion #2, concerned with student knowledge of and abilities in:

b. Apply/adapt knowledge to emerging applications of math, science, engineering and technology

( “…career and professional accomplishments that the program is preparing graduates to achieve during the first few years following graduation.”)

ECET Program Outcomes

(“…units of knowledge or skill students are expected to acquire from the program to prepare them to achieve the program educational objectives.”)

1. Be able to specify, design, analyze, modify and implement hardware, software, and integrated systems applications

2. Be able to apply knowledge gained in basic science, electrical and computer engineering technology and mathematics to solutions of real world applications using creative problem-solving skills

4. Be able to work productively in teams, have team building skills as well as have management and leadership skills

5. Understand the importance of continuous (life-long) learning and be aware of available resources to keep skills current as technologies continuously change.

7. Be able to work effectively in a diverse environment while following accepted professional, ethical and social standards.

8. Understand the importance of a commitment to quality and continuous improvement.

Monday	1:00 - 2:25
Thursday	11:30 - 12:55

Grading:	Homework	10 %	Tests	25 %
	Projects	25 %	Final Exam	30 %
	Professional Society Meeting attendance	5 %	Technical Journal Report	5 %

Outcome # 1. Students will have the ability to analyze and design basic combinational logic circuits.
Strategies & Actions	TAC Criterion 2	Program Outcomes	Assessment Methods
Fundamentals of combinational logic are covered in lectures, homework, and projects 1 - 3. In teams, students use the software, write reports, and participate in class exercises.	a – g, k	1,2,3,4,7, 8	Tests, Homework, and reports of the projects are graded.
Outcome # 2. Students will have the ability to analyze and design basic sequential logic circuits.
Strategies & Actions	TAC Criterion 2	Program Outcomes	Assessment Methods
Fundamentals of sequential logic are covered in lectures, homework, and project 4. In teams, students use the software, write reports, and participate in class exercises.	a – g, k	1,2,3,4,7,8	Tests, Homework, and reports of the projects are graded.
Outcome # 3. Students will have the ability to simulate and troubleshoot simulations of combinational and sequential logic. They will be able to create designs using vhdl.
Strategies & Actions	TAC Criterion 2	Program Outcomes	Assessment Methods
Fundamentals of the software are covered in lectures, homework, and project 4. In teams, students use the software, write reports, and participate in class exercises.	a – g, k	1,2,3,4,7,8	Tests, Homework, and reports of the projects are graded.
Outcome # 4. Students will appreciate the value of professionalism and timeliness in their class work, projects and career as well as the usefulness of, and role of professional societies in, lifelong learning.
Strategies & Actions	TAC Criterion 2	Program Outcomes	Assessment Methods
Homework and project reports are on a strict schedule and must follow professional standards in their content and structure. Students are required to submit a brief report on their attendance at a professional society meeting and a brief report from a technical journal article.	g, h, i, k	3, 5, 6,8	Reports graded.

Class Hours

Office Hours (GITC 2101)

Snow Phone

ECET Program Outcomes